This invention relates generally to integrated circuits and in particular to systems and methods for improving signal propagation on integrated circuit transmission lines.
The semiconductor industry is moving to smaller feature sizes and larger die sizes. As such, integrated circuits incorporate relatively long transmission lines. Transmitting signals over relatively long integrated circuit transmission lines may cause an unacceptable delay that is attributable to the capacitance associated with the transmission lines. Repeaters, also referred to as repeater amplifiers or buffer drivers, have been placed in line along the transmission line in an attempt to alleviate this delay problem. The repeater boosts the signal edge rate enough to compensate for a logic delay introduced by the repeater. One example of a repeater is an inverting amplifier or buffer. Signal propagation problems associated with the inverting amplifier include those that relate to propagation speed and power consumption.
The inverting amplifier encounters a delay during transitions between logic potentials. The dotted line in FIG. 1 shows by way of example a simulation of an inverting amplifier in which the output is at an initially low logic potential, and then is driven to a high logic potential to make a full or complete low-to-high logic transition. The delay associated with making a complete low-to-high logic transition, in on example of the inverting amplifier, is about 400 picoseconds. As viewed by the inverting amplifier, the input signal is considered to be random as it can require the output to be driven high or low without advance notice. Thus, the amplifier should be able to quickly drive the output to either a high or low potential. However, although no delay is incurred when the output remains at its previous logic potential, the propagation speed for a transmission line system is limited by the worse case delay that occurs when the input signal requires a complete high-to low or low-to-high logic transition.
Not only does the complete voltage potential transition create a delay, but it also requires a power supply to provide the current to raise the voltage from a low logic potential to a high logic potential on one of the two sides of the inverting amplifier. When the voltage potential transitions from the high logic potential back to the low logic potential, the charge is effectively dumped to the bus by shorting the high side of the inverting amplifier to ground. The power supply again provides the required current for the voltage potential to transition from the low logic potential back to a high logic potential. FIG. 12 illustrates an extreme example wherein a conventional full-logic transition wave form switches between low and high logic potentials every cycle. The repetitive charging and dumping for each complete voltage potential transition has a relatively high instantaneous power consumption demand.
Therefore, there is a need in the art to provide a system and method for improving signal propagation on integrated circuit transmission lines which overcomes these problems.
The above mentioned problems are addressed by the present subject matter and will be understood by reading and studying the following specification. The present subject matter improves signal propagation, particularly on an integrated circuit transmission line. A repeater divides or segments a transmission line or wire track into a first line and a second line. The repeater receives an active segment, i.e. a signal that makes transitions between high and low logic potentials, signal on the first line and transmits an inverted signal on the second line such that one of these lines is at a high logic potential and the other line is at a low logic potential. The signal has cycles that are comprised of an inactive portion and an active portion. In one embodiment, a control signal defines the duration of the active portion and inactive portion of the cycles. The signal makes the transition to either the high or low logic potential during the active portion. Charge is shared between the two lines during the inactive portion of the cycle such that, upon completion of the inactive portion, both the first line and the second line are at starting potentials which are substantially the same and which are between the low logic potential and the high logic potential. The starting potential is the potential that is on the line at the beginning of the active portion of the cycle; i.e. at the beginning of the signal transition to either the high or low logic potential. Rather than by beginning the logic transition from either the low logic potential or the high logic potential and then making a full transition to the other logic potential, the worse-case logic transition delay for the transmission line is shortened by beginning the logic transition from this starting potential and then making a transition to either the low logic potential or high logic potential.
One aspect provides an integrated circuit transmission line repeater. The repeater generally comprises an inverting amplifier and an equilibration circuit. The inverting amplifier has an input connected to a first line and an output connected to a second line. The amplifier receives an input signal on the first line at a first logic potential and transmits an output signal on the second line at a second logic potential during an active portion of a cycle. The equilibration circuit electrically isolates the first line and the second line and shorts the first line to the second line during an inactive portion of the cycle such that upon completion of the inactive portion, the first line and the second line will be at substantially the same starting potential between the low logic potential and the high logic potential.
Another aspect provides a method for signaling over a transmission line that generally comprises a first process that is performed during an active portion of a cycle, and a second process that is performed during an inactive portion of the cycle. The first process includes receiving an input signal on a first line at a first logic potential, and transmitting an inverted output signal on a second line at a second logic potential. The second process includes isolating both the first line and the second line, and electrically shorting the first line to the second line to provide substantially equal potentials between the first logic potential and the second logic potential.